feat(languages): add vhdl (@joelievt)#7924
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monkeytypegeorge
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Leonabcd123
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May 7, 2026
| "code_visual_basic", | ||
| "code_arduino", | ||
| "code_systemverilog", | ||
| "code_vhdl", |
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Per the languages documentation:
"Go to packages/schemas/src/languages.ts and add your new language name at the end of the LanguageSchema enum."
Please move it to the end of the enum (also move it to the end of the code group in frontend/src/ts/constants/languages.ts).
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Description
Adds VHDL. There's already SystemVerilog, so this completes the big HDL pair. Word list is IEEE 1076-2008 reserved words plus a few stdlib identifiers.
Also added some quotes, which are listings from Free Range VHDL.
Checks
packages/schemas/src/languages.tsfrontend/src/ts/constants/languages.tsfrontend/static/languages